This invention relates to a method for making a high current handling driver or power transistor in a silicon integrated circuit along with CMOS and other small signal transistors, and more particularly relates to integrated vertical power transistors wherein an N+ buried layer and an N+ plug region provide a low resistivity path for the high transistor load current.
The maximum current that an integrated power transistor can handle safely is directly related to the maximum temperature that is tolerable before it is destroyed. Elevated device temperature is attributable to forward (load) current, high parasite-transistor-current and current at voltage breakdown. As the forward (load) current that a switched driver transistor will be required to carry increases the more important becomes the power dissipation due to forward-current voltage-drop or V.sub.SAT across the transistor which is strongly related to the on-resistance through the transistor.
In vertical integrated power transistors, the on-resistance is made as low as possible by forming the transistor in an epitaxial pocket with a heavily doped buried layer that is contacted by a conductive plug accessible at the epitaxial-layer surface.
An NPN power transistor of this kind is described by Zunino in U.S. Pat. No. 4,646,124 issued Feb. 24, 1987 and assigned to the same assignee as is the present invention. Here the N+ buried layer makes broad contact with the N-epitaxial pocket which serves as the power transistor collector.
Another integrated vertical transistor, a power DMOS transistor, is described by Huie et al in a patent application Ser. No. 281,593, filed Dec. 9, 1988 and assigned to the same assignee as is the present invention. This vertical DMOS power transistor handles a high load current and operates at a relatively high voltage (65 volts).
Transistor voltage breakdown is directly related to epitaxial layer thickness. However, the difficulty and cost (e.g. in silicon real estate) of providing a low resistivity plug through the epitaxial layer grows as the epitaxial layer thickness increases. The heavy concentrations of dopants for forming the plug must diffuse further to extend through the epitaxial layer, but also diffuse further laterally to occupy more die surface area.
In U.S. Pat. No. 4,458,158 to Mayrand and assigned to the same assignee as is the present invention there is described another integrated vertical power transistor in which two epitaxial layers are employed. Here, a small auxiliary buried N+ layer is registered with an outer surface N+ plug diffusion that together reach through both epitaxial layers to a main N+ buried layer that serves as collector of the power NPN. However, the double epitaxial layer process may in some cases nullify the cost advantage of the space saving two-component N+ plug.
It is therefore an object of this invention to provide a low cost integrated circuit including small signal transistors with a vertical power transistor with low forward resistance and high current handling capability.
It is another object of this invention to provide such an integrated power transistor having an N+ plug with an abnormally high dopant concentration.
It is a further object of this invention to provide a low cost method for providing such an integrated circuit in which the N+ plug is self-aligned with the power transistor device area.